The invention relates to an error processing circuit for a receiving location of a system for transferring binary data in the form of pulse sequences.
One form of a data transmission system is a CAN system. The term CAN stands for Controller Area Network. Further details in this respect can be found in the book xe2x80x9cController Area Network: CANxe2x80x9d by Konrad Etschberger, Carl Hanser Publishing House 1994, ISBN No. 3-446-17596-2. Of interest in the present context are the sections on Protocol Properties on pages 25 and 26 and Data/Frame Format on pages 37 to 43.
Such CAN systems are employed for example in the field of motor vehicles.
There is a common supply voltage source for the CAN system, e.g., in the form of a motor vehicle battery delivering for instance a battery voltage of 12 V. Furthermore, each network node has an individual operating voltage source associated with each network node, which produces from the supply voltage a regulated operating voltage feeding the respective network node. Each operating voltage source delivers an operating potential, for example of 5 V, at a first terminal and a reference potential, for example ground potential or 0 V, at a second terminal.
The transmitting part of a network node has two resistors and two controllable electronic switches connected to the two lines of the double-line bus. One of these lines is connected via a first one of these resistors to the operating potential (5 V) and via a first one of these switches to the reference potential (0 V). The other line is connected via the second resistor to the reference potential (0 V) and via the second switch to the operating potential (5 V). For transmitting digital communications, the two switches are controlled synchronously either to a conducting state or to a non-conducting state. When the switches are controlled to the non-conducting state, the operating potential is present on one line and the reference potential is present on the other line. This switch state, for example, has the logic value xe2x80x9c1xe2x80x9d associated therewith. When the switches are controlled to the conducting state, the reference potential is present on one line and the operating potential is present on the other line. This switch state then has the logic value xe2x80x9c0xe2x80x9d associated therewith.
As the transmitting parts of all network nodes capable of transmission are connected in parallel with respect to the two lines, the potential ratio on the two lines, which is associated with logic value xe2x80x9c0xe2x80x9d, can be produced by closing the two switches of each of the transmissive network nodes. On the other hand, the non-conducting state of the two switches of each network node can be covered up by the conducting state of the two switches of another network node. For this reason, the logic value associated with a closed switch pair (logic value xe2x80x9c0xe2x80x9d) is referred to as dominant and the logic value associated with a non-conducting switch pair (logic value xe2x80x9c1xe2x80x9d) is referred to as recessive.
The receiving part of each network node capable of reception comprises a comparator comparing the respective potentials on the two lines with each other. Upon reception of a recessive bit (logic value xe2x80x9c1xe2x80x9d), for example, a positive potential is created at the output of the comparator, which has the logic value xe2x80x9c1xe2x80x9d associated therewith. Upon reception of a dominant bit (logic value xe2x80x9c0xe2x80x9d), a potential corresponding to the reference potential is present at the output of the comparator, which then has the logic value xe2x80x9c0xe2x80x9d associated therewith. The comparator thus constitutes a decoder for the potential relationships corresponding to the respective transmitted bit on both lines.
For reasons of redundance, the two lines are used in addition to system ground. The message information corresponding to the potential value of the respective bit transmitted is thus transferred both via the one line and via the other line. In case of failure of one of the lines, the further transmission operation can be restricted to the non-failed line. For detecting line failures, two additional comparators are provided, one thereof comparing the potential of one line and the other one thereof the potential of the other line with a mean potential that is between the operating potential and the reference potential.
There can occur different line failures or line faults or errors, for instance, in the form of short-circuits between the two lines, short-circuits towards system ground, short-circuits towards the operating potential source, short-circuits towards the supply voltage source or in the form of open lines. There are line errors that do not hinder secure decoding of the communications transmitted. There are other line errors against which specific measures need to be taken in order to still render possible correct decoding. More details in this respect can be found in DE 195 23 031 A1.
In a CAN network, the messages or communications are transferred in the form of pulse sequences or frames spaced apart in time. The usual CAN protocol provides that a minimum distance in time is present between the individual frames and that within one frame there must be no more than 11 recessive or dominant bits in succession.
It is known from DE 196 23 031 A to use, for a decoder on the receiving side, the three comparators mentioned hereinbefore, to examine the output signals thereof for the presence of specific line errors with the aid of an error recognition circuit and to decide, depending on the result of this comparison, the output of which one of these three comparators is to be connected to a data output of the receiving location via a multiplexer controlled by the error recognition circuit. When the comparator comparing the potential values of the two lines delivers the potential value of the dominant logic value xe2x80x9c0xe2x80x9d for a longer duration than permitted according to the CAN protocol, it is assumed that the two lines are either short-circuited with respect to each other or the first line has a short-circuit towards system ground, and the comparator used as data output is that one which compares the potential of the second line to a mean potential value. This means, as soon as the comparator comparing the potential values permanently has the dominant logic value xe2x80x9c0xe2x80x9d beyond the duration permitted by the CAN protocol, recourse is taken to the potential changes on the second line for decoding of the data received.
However, there are line faults or errors that are recognizable by a permanent dominant logic value xe2x80x9c0xe2x80x9d at the output of the comparator comparing the potential values of the two lines, but in case of which there are no more potential changes taking place on the second line. Such a case is present when the second line displays a short-circuit towards the operating voltage source (5 V) associated with or inherent with each network node. In case of such a line error too, the known circuit arrangement also takes recourse to the output of the comparator monitoring the second line with respect to potential changes. And as there are no more potential changes taking place, data decoding fails.
The invention provides an error processing circuit for a receiving location of a system for transferring binary data in the form of pulse sequences, wherein the system has a number of receiving locations connected via a double-line bus having a first line and a second line. A first logic value of the binary data is represented by a high potential value on the first line and a low potential value on the second line, and a second logic value of the binary data is represented by a low potential value on the first line and a high potential value on the second line. Within each pulse sequence, there must be no more than a predetermined number of equal data bits in succession.
The receiving location includes a data output, a decoder having three decoder outputs, a first decoder output associated with both lines delivers a first decoder output signal dependent on the difference between the potential values of both lines, a second decoder output associated with the first line delivers a second decoder output signal dependent on the difference between the potential value of the first line and a first mean potential value, and a third decoder output associated with the second line delivers a third decoder output signal dependent on the difference between the potential value of the second line and a second mean potential value, the first mean potential value and the second mean potential value each lying between the high potential value and the low potential value. In the error-free case and upon occurrence of line errors of a first error group with a line error on one of the two lines, at least the first decoder output delivers properly decoded data, and upon occurrence of a second error group with a line error on one of the two lines, only the decoder output associated with the error-free other line still delivers properly decoded data.
The circuit further includes a line condition detector circuit, by means of which error-free line conditions as well as line errors of the first line and line errors of the second line can be detected depending on the decoder output signals, and changeover control signals can be delivered depending on the particular detection result; and a controllable changeover switch by means of which the data output, upon detection of line conditions in which only the second or third decoder output delivers properly decoded data, is connected to this decoder output and otherwise to the first decoder output.
The error processing circuit not only detects whether the decoder, in connection with the comparison of the potential values of the two lines, permanently delivers the dominant logic value xe2x80x9c0xe2x80x9d and in this case switches over to evaluation of the potential values of the second line only, but the error consideration and error processing always take into consideration the line conditions of both lines with respect to still existing potential changes. This provides the possibility that in case of any line error in which a comparison of the potential values of the two lines no longer allows data decoding, recourse can be taken to switch to one of the two lines that still exhibits potential changes.
With the line error mentioned, in which the second line is short-circuited with the operating voltage of the network node considered and in which the known error processing circuit no longer permits data decoding since it switches over just to this error-inflicted line in case of data decoding, the invention provides for data decoding switching over to the first line that still has potential changes.
The line condition detector circuit may comprise: a first logic circuit linking the first decoder output signal and the second decoder output signal and delivering a first logic signal; a second logic circuit linking the first decoder output signal and the third decoder output signal and delivering a second logic signal; a first time measuring circuit measuring the first logic signal and a second time measuring circuit measuring the second logic signal, by means of which a time measurement of logic signal values of the first and second logic signals, respectively, which may mean a line error, is carried out and a first and second line error signal, respectively, is generated when such a logic signal value, as of occurrence thereof, has a longer duration than a duration corresponding to the predetermined number of equal data bits; and a third logic circuit linking the two line error signals, said third logic circuit linking the two line error signals so as to provide the changeover control signal.
The two time measuring circuits provide the possibility of time masking potential value conditions on the two lines that would be interpreted as line errors although they may occur within the protocol of the data transmission system with error-free line, until it is established according to the protocol that these really must be line errors.
The first, second, and third logic circuits may each be composed of a NOR element, and the fourth logic circuit may be an AND element having an inverting input and a non-inverting input. The two time measuring circuits may each be constituted by a counter which counts clock pulses fed thereto via a counting clock input, as long as it is released to count via a counting release/resetting input. A first logic value, for example xe2x80x9c1xe2x80x9d, releases the counter for counting, and a second logic value, in the present example xe2x80x9c0xe2x80x9d, resets the counter to an initial counting state, preferably to a count of 0. Potential value patterns on the two lines, which may occur in case of line errors, release counting of the one and/or the other counter and, in case they last longer than the period of time permitted by the protocol of the data transmission system, result in a potential change at the output of the respective counter, which is evaluated by the third logic circuit having the third NOR element and the AND element.
The decoder, in a maimer known per se, may be composed of three comparators, of which a first one compares the potential values of the two lines with each other and the two other ones compare the potential value of the first line and the second line, respectively, with a mean potential value lying between the high potential value and the low potential value which are transmitted via the two lines in case of error-free lines.
The controllable changeover switch may be composed of a multiplexer having three inputs, each one thereof being connected to one of the three comparator outputs, and having a multiplexer output connected to the data output of the receiving location, as well as three changeover control inputs. Of the latter ones, one is connected to the counter output of the first counter, a second one is connected to the output of the third NOR element, and a third one is connected to the output of the AND element.
The multiplexer and the third logic circuit of the line condition detector circuit are composed and connected in such a manner that the multiplexer output connected to the data output of the receiving location is connected to the output of the first comparator comparing the potential values of both lines with each other, always at such times when both lines are error-free or when such line errors are present with which the comparator output of the first comparator still delivers potential changes from which the data transmitted can be derived. Construction and connection of multiplexer and third logic circuit furthermore are selected such that, in case of line errors with which there are no longer potential changes occurring at the output of the first comparator and thus no more logic values changes take place, the data output of the receiving location is connected to the comparator output of the second or third comparator, depending on whether there still are potential changes and thus logic value changes occurring with the line error involved at the comparator output of the second or third comparator.